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? semiconductor components industries, llc, 2013 november, 2013 ? rev. 3 1 publication order number: ncd9830/d ncd9830 8-bit, 8-channel adc with i 2 c serial interface the ncd9830 is a two ? wire serially programmable analog to digital converter. it can monitor 8 analog inputs to 8 ? bit resolution. each channel is selected using the i 2 c interface and can also be configured to be a single ended or differential type measurement. communication with the ncd9830 is accomplished via the i 2 c interface which is compatible with industry standard protocols. through this interface configuration of the ncd9830 is achieved. this allows the user to read the current measurement for the selected channel, change to an external reference and modify the measurement type (single ended or differential). the ncd9830 is available in a 16 ? lead tssop package and operates over a wide supply range of 2.7 to 5.5 v. features ? 8 ? bit adc ? 8 single ? ended inputs/4 differential inputs ? 2.7 v to 5.5 v operation ? built in 2.5 v reference ? 2 address selection pins ? low power consumption ? i 2 c compliant interface ? standard, fast and high speed modes ? these devices are pb ? free, halogen free/bfr free and are rohs compliant marking diagram tssop ? 16 dt suffix case 948f http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information 1 16 ncd 9830 alyw 1 16 a = assembly location l = wafer lot y = year w = work week = pb ? free package (*note: microdot may be in either location)
ncd9830 http://onsemi.com 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ch0 sda a1 gnd figure 1. pin configuration (top view) ch1 ch2 ch3 ch4 ch5 ch6 ch7 v dd scl a0 com ref in /ref out 8 ? bit a ? to ? d converter analog mux i2c interface 14 15 10 v dd gnd sda scl a1 ch0 ch1 a0 16 ch2 ch3 9 5 3 12 7 2 6 1 4 13 ch6 ch5 ch4 2.5v ref temporary data storage ncd9830 8 ch7 1 1 com refin/refout figure 2. functional block diagram of ncd9830
ncd9830 http://onsemi.com 3 table 1. pin function description pin no. pin name description 1 ch0 analog input. 2 ch1 analog input. 3 ch2 analog input. 4 ch3 analog input. 5 ch4 analog input. 6 ch5 analog input. 7 ch6 analog input. 8 ch7 analog input. 9 gnd power supply ground. 10 ref in / ref out internal 2.5 v reference or external reference input. 11 com common to analog input channel (typically connected to gnd). 12 a0 functions as an i 2 c address selection bit. 13 a1 functions as an i 2 c address selection bit. 14 scl serial clock input. open ? drain pin; needs a pull ? up resistor. 15 sda i 2 c serial bi ? directional data input/output. open ? drain pin; needs a pull ? up resistor. 16 v dd positive supply voltage. bypass to ground with a 0.1 f bypass capacitor. table 2. absolute maximum ratings rating symbol value unit supply voltage (v dd ) v dd ? 0.3 to +6.5 v analog input voltage to gnd ? 0.3 to v dd +0.3 v voltage on any pin (not analog inputs) v dd v maximum junction temperature t j(max) 150.7 c storage temperature range t stg ? 65 to 160 c esd capability, human body model (note 1) esd hbm 3 kv esd capability, machine model (note 1) esd mm 150 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristics and application information for safe operating area. table 3. operating ranges rating symbol min max unit operating supply voltage v dd 2.7 5.5 v operating ambient temperature range t a ? 40 125 c 2. refer to electrical characteristics and application information for safe operating area.
ncd9830 http://onsemi.com 4 table 4. electrical characteristics 2.7 v t a = ? 40 c to +125 c, v dd = 2.7 v, v ref = 2.5 v, scl freq = 3.4 mhz, unless otherwise noted. parameter test conditions min typ max unit analog input full scale input range positive and negative input 0 v ref v max input range positive input ? 0.2 v dd + 0.2 v negative input ? 0.2 0.2 v capacitance 25 pf leakage current 1 a system performance no missing codes 8 bits integral linearity error 0.1 0.5 lsb differential linearity error 0.1 0.5 lsb offset error +0.5 +1 lsb offset error match 0.05 0.25 lsb gain error 0.1 0.5 lsb gain error match 0.05 0.25 lsb noise 100 vrms power supply rejection 72 db sampling dynamics throughput frequency high speed mode: scl = 3.4 mhz 70 ksps fast mode: scl = 400 khz 10 ksps standard mode: scl = 100 khz 2.5 ksps conversion time 5 s ac accuracy total harmonic distortion v in = 2.5 vpp at 1 khz ? 72 db signal ? to ? ratio v in = 2.5 vpp at 1 khz 50 db signal ? to ? (noise+distortion) ratio v in = 2.5 vpp at 1 khz 49 db spurious free dynamic range v in = 2.5 vpp at 1 khz 68 db channel to channel isolation 90 db voltage reference output range 2.475 2.5 2.525 v internal reference drift 15 ppm/ c output impedance internal reference on 700 internal reference off 1 g quiescent current internal reference on, scl and sda pulled high 850 a voltage reference input range 0.05 v dd v resistance 1 g current drain high speed mode: scl = 3.4 mhz 20 a digital input/output
ncd9830 http://onsemi.com 5 table 4. electrical characteristics 2.7 v t a = ? 40 c to +125 c, v dd = 2.7 v, v ref = 2.5 v, scl freq = 3.4 mhz, unless otherwise noted. parameter unit max typ min test conditions digital input/output logic levels: v ih 0.7 x v dd v dd + 0.5 v v il 0 0.3 x v dd v v ol minimum 3 ma sink current 0.4 v input leakage: i ih v ih = v dd + 0.5 10 a i il v il = 0 v ? 10 a power supply requirements v dd 2.7 3.6 v quiescent current high speed mode: scl = 3.4 mhz 225 320 a fast mode: scl = 400 khz 100 a standard mode: scl = 100 khz 60 a power dissipation high speed mode: scl = 3.4 mhz 675 1000 w fast mode: scl = 400 khz 300 w standard mode: scl = 100 khz 180 w power down mode (wrong address selected) high speed mode: scl = 3.4 mhz 70 a fast mode: scl = 400 khz 25 a standard mode: scl = 100 khz 6 a full power down scl, sda pulled high 400 3000 na table 5. electrical characteristics 5 v t a = ? 40 c to +125 c, v dd = 5 v, v ref = 5 v (external), scl freq = 3.4 mhz, unless otherwise noted. parameter test conditions min typ max unit analog input full scale input range positive and negative input 0 v ref v max input range positive input ? 0.2 v dd + 0.2 v negative input ? 0.2 0.2 v capacitance 25 pf leakage current 1 a system performance no missing codes 8 bits integral linearity error 0.1 0.5 lsb differential linearity error 0.1 0.5 lsb offset error +0.5 +1 lsb offset error match 0.05 0.25 lsb gain error 0.1 0.5 lsb gain error match 0.05 0.25 lsb noise 100 vrms power supply rejection 72 db
ncd9830 http://onsemi.com 6 table 5. electrical characteristics 5 v t a = ? 40 c to +125 c, v dd = 5 v, v ref = 5 v (external), scl freq = 3.4 mhz, unless otherwise noted. parameter unit max typ min test conditions sampling dynamics throughput frequency high speed mode: scl = 3.4 mhz 70 ksps fast mode: scl = 400 khz 10 ksps standard mode: scl = 100 khz 2.5 ksps conversion time 5 s ac accuracy total harmonic distortion v in = 2.5 vpp at 1 khz ? 72 db signal ? to ? ratio v in = 2.5 vpp at 1 khz 50 db signal ? to ? (noise+distortion) ratio v in = 2.5 vpp at 1 khz 49 db spurious free dynamic range v in = 2.5 vpp at 1 khz 68 db channel to channel isolation 90 db voltage reference output range 2.475 2.5 2.525 v internal reference drift 15 ppm/ c output impedance internal reference on 700 internal reference off 1 g quiescent current internal reference on, scl and sda pulled high 1300 a voltage reference input range 0.05 v dd v resistance 1 g current drain high speed mode: scl = 3.4 mhz 20 a digital input/output logic levels: v ih 0.7 x v dd v dd + 0.5 v v il 0 0.3 x v dd v v ol minimum 3 ma sink current 0.4 v input leakage: i ih v ih = v dd + 0.5 10 a i il v il = 0 v ? 10 a power supply requirements v dd 4.75 5.25 v quiescent current high speed mode: scl = 3.4 mhz 750 1000 a fast mode: scl = 400 khz 300 a standard mode: scl = 100 khz 150 a power dissipation high speed mode: scl = 3.4 mhz 3.75 5 mw fast mode: scl = 400 khz 1.5 mw standard mode: scl = 100 khz 0.75 mw power down mode (wrong address selected) high speed mode: scl = 3.4 mhz 400 a fast mode: scl = 400 khz 150 a standard mode: scl = 100 khz 35 a full power down scl, sda pulled high ta = ? 40 c to 85 c ta = ? 40 c to 125 c 400 400 3000 3500 na
ncd9830 http://onsemi.com 7 timing characteristics table 6. i 2 c timing parameter (note 3) symbol conditions min max unit clock frequency f scl standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 10 100 400 3.4 1.7 khz khz mhz mhz bus free time t buf standard mode fast mode 4.7 1.3 s s start hold time (note 4) t hd;sta standard mode fast mode high speed mode 4.0 600 160 s ns ns scl low time t low standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 4.7 1.3 160 320 s s ns ns scl high time t high standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 4.0 600 60 120 s ns ns ns start setup time t su;sta standard mode fast mode high speed mode 4.7 600 160 s ns ns data setup time (note 5) t su;dat standard mode fast mode high speed mode 250 100 10 ns data hold time (note 6) t hd;dat standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 0 0 0 0 3.45 0.9 70 150 s s ns ns scl rise time t rcl standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 20+0.1c b 10 20 1000 300 40 80 ns ns ns ns scl rise time (after repeated start) t rcl1 standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 20+0.1c b 10 20 1000 300 80 160 ns ns ns ns scl fall time t fcl standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 20+0.1c b 10 20 300 300 40 80 ns ns ns ns sda rise time t rda standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 20+0.1c b 10 20 1000 300 80 160 ns ns ns ns sda fall time t fda standard mode fast mode high speed mode (100 pf) high speed mode (400 pf) 20+0.1c b 10 20 300 300 80 160 ns ns ns ns stop setup time t su;sto standard mode fast mode high speed mode 0.4 600 160 s ns ns capacitive load c b 400 pf 3. guaranteed by design, but not production tested. 4. time from 10% of sda to 90% of scl. 5. time for 10%or 90% of sda to 10% of scl. 6. a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the fall ing edge of scl.
ncd9830 http://onsemi.com 8 table 6. i 2 c timing parameter (note 3) unit max min conditions symbol glitch immunity t sp fast mode high ? speed mode 50 10 ns ns noise margin at high level v nh standard mode fast mode high speed mode 0.2 v dd v noise margin at low level v nl standard mode fast mode high speed mode 0.1 v dd v 3. guaranteed by design, but not production tested. 4. time from 10% of sda to 90% of scl. 5. time for 10%or 90% of sda to 10% of scl. 6. a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the fall ing edge of scl. figure 3. serial interface timing
ncd9830 http://onsemi.com 9 typical characteristics t a = +25 c, v dd = +2.7 v, v ref = external 2.5 v, f sample = 50 khz, unless otherwise stated. 0 frequency (khz) figure 4. fft vs. frequency 0 amplitude (db) 0 output code figure 5. inl vs. code (ext ref) 0.5 inl (lsb) 25 250 50 75 100 125 150 225 200 175 0.4 0.3 0.2 0.1 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 0 output code figure 6. dnl vs. code (ext ref) 0.5 dnl (lsb) 25 250 50 75 100 125 150 225 200 175 0.4 0.3 0.2 0.1 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 0 output code figure 7. inl vs. code (int ref) 0.5 inl (lsb) 25 250 50 75 100 125 150 225 200 175 0.4 0.3 0.2 0.1 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 0 output code figure 8. dnl vs. code (int ref) 0.5 dnl (lsb) 25 250 50 75 100 125 150 225 200 175 0.4 0.3 0.2 0.1 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 ? 50 temperature ( c) figure 9. change in offset vs. temperature 0.2 delta from 25 c (lsb) ? 30 130 0.15 0.1 0.05 0 ? 0.05 ? 0.1 ? 0.15 ? 0.2 ? 10 110 90 70 50 30 10 510152025 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100
ncd9830 http://onsemi.com 10 typical characteristics t a = +25 c, v dd = +2.7 v, v ref = external 2.5 v, f sample = 50 khz, unless otherwise stated. ? 50 temperature ( c) figure 10. change in gain vs. temperature 0.2 delta from 25 c (lsb) ? 30 130 0.15 0.1 0.05 0 ? 0.05 ? 0.1 ? 0.15 ? 0.2 ? 10 110 90 70 50 30 10 ? 45 temperature ( c) figure 11. internal v ref vs. temperature 2.55 internal reference (v) ? 25 95 ? 575 35 15 2.5375 2.525 2.5125 2.5 2.4875 2.475 2.4625 2.45 2.4375 2.425 2.4125 ? 50 temperature ( c) figure 12. power ? down supply current vs. temperature 1000 supply current (na) ? 30 130 ? 10 110 90 70 50 30 10 900 800 700 600 500 400 300 200 100 0 ? 50 temperature ( c) figure 13. supply current vs. temperature ? 30 130 ? 10 110 90 70 50 30 10 400 350 300 250 200 150 100 supply current ( a) 10 i 2 c bus rate (khz) figure 14. supply current vs. i 2 c bus rate 300 supply current ( a) 250 200 150 100 50 0 100 1000 10000 0 turn ? on ? time ( s) figure 15. internal v ref vs. turn ? on time 3000 3 internal v ref (v) 2.5 2 1.5 1 0.5 0 ? 0.5 500 1000 1500 2000 2500 no cap 1 f 55
ncd9830 http://onsemi.com 11 circuit information operation the ncd9830 is a low power successive approximation adc with a built in 8 channel multiplexer and 8 bit resolution. the 8 bit resolution assures high noise immunity and fast digitization that makes this device suitable for medium to high speed applications. the device internal circuitry operates at speed higher than the conversion time of the device because of the binary algorithm used. the algorithm is based on approximating the input signal by comparing with successive analog signal generated from the built in dac. the device can be operated at supply voltages of 2.7 v and 5 v. the liberty of supply voltage variation must be used with appropriate reference voltage selection. the ncd9830 internal dac can be configured with an externally (50 mv ? 5 v) supplied or an internally internally generated reference voltage of 2.5 v. however, to avail full dynamic range an external reference of 5 v must be used while operating the device at 5 v supply voltage. the internal 2.5 v reference voltage is sufficient for full dynamic range while operating the device at 2.7 v. the value of each output bit is evaluated on the basis of output of the comparator. the converter requires n conversion periods to give n bit digital output of the input analog signal. the sar register stores the digital equivalent bits of the input analog signal and can be read by the master device using an i 2 c interface. the main building block of the device are i. digital to analog converter ii. comparator iii. digital logic digital to analog converter a charge scaling dac is used due to its compatibility with the switch capacitor circuits. the dac operation consists of two phases called acquisition phase and the conversion phase. the acquisition phase is analogous to sample and hold circuit while the conversion phase is the process of conversion of the internal digital word in to an analog output. acquisition phase: the top plates of all the capacitors on the array are connected to the ground and the bottom plates are connected to the applied voltage vin. thus there is a charge proportional to input voltage on the capacitor array. after acquisition the top and bottom plates are disconnected from their respective connections. figure 16. the acquisition phase of a typical adc c 2c 4c 8c 128c vin conversion phase: the conversion phase is administered by a two phase non overlapping clock with phases 1 and 2 respectively. during 1 the bottom plates of all the capacitors are grounded i.e the top plates of all the capacitors are now vin times higher than the ground. as the conversion process starts the digital con trol sets all the bits zero except the msb in the sar register. during the 2 the capacitors associated with msb is connected to vref while others are connected to ground. in this way the dac generates analog voltage of magnitude vref/2. the analog output of dac is compared with the input analog signal. the digital control logic sets the msb to 1 if comparator output is high and 0 otherwise. thus the first step of sar algorithm decides whether the input signal is greater or less than vref/2. the approximation process is then run again with the msb in its proven value and the next lower bit is set to 1. this gives a general direction path and the remaining approximations will converge the output in this direction. figure 17. the conversion phase of a typical adc c 2c 4c 8c 128c vref vin 2 1 2 1 2 1 2 1 comparator a switch capacitor comparator is used to alleviate the effects of input offset voltage. the issue of charge injection is controlled by using fully differential topology.
ncd9830 http://onsemi.com 12 digital logic the function of the digital logic is to generate the binary word to be compared with the input analog signal in each approximation cycle. the result of each approximation cycle is stored in the sar register. in short the digital logic determines the value of each output bit in a sequential manner base don the output of the comparator. analog channels the analog inputs (ch0 ? ch7) are multiplexed into the on ? chip successive approximation, analog ? digital converter. this has a resolution of 8 bits. the basic input range is 0 v to v dd . when not performing a conversion or being addressed, the adc core is powered off to preserve power. the internal clock is also powered off. reference the ncd9830 can operate with either its own internal 2.5 v reference or an externally supplied reference. if using a 5 v supply then an external 5 v reference needs to be used in order to provide the full range for the 0 to v dd analog input channels. the internal 2.5 v reference will still be sufficient to provide full dynamic range for the 0 to v dd analog input channels. serial bus interface control of the ncd9830 is carried out via the i 2 c bus. the ncd9830 is connected to this bus as a slave device, under the control of a master device. the ncd9830 has a 7 ? bit serial bus address. the upper 5 bits of the device address are 10010. the lower 2 bits are set by pins 12 and 13. table 7 shows the 7 ? bit address for each of the pin states. the address pins can be connected to v dd or gnd and the address is set by the state of these pins on power up. the logic of this address pin is monitored on power up on the first i 2 c transaction, more precisely , on the low ? to ? high transition at the beginning of the eighth scl pulse. the ability to make hardwired changes to the i 2 c slave address allows the user to avoid conflicts with other devices sharing the same i 2 c address, for example, if more than one ncd9830 is used in a system. ncd9830 is compatible to all three operating modes of i 2 c interface i.e standard (100 khz), fast (400 khz) and high speed (3.4 mhz) modes. table 7. i 2 c address options a1 a0 address 0 0 0x48 0 1 0x49 1 0 0x4a 1 1 0x4b the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high ? to ? low transition on the serial data line sda while the serial clock line, scl, remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next eight bits, consisting of a 7 ? bit address (msb first) plus an r/w bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, the master will write to the slave device. if the r/w bit is a 1, the master will read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low ? to ? high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition. command byte ncd9830 can be operated in different modes depending on the internal power state of different circuit sections and input configuration (single ended or dif ferential). command byte also contains three channel select c x bits of the internal eight channel multiplexer. the format of the command byte is as follows the 8 bit command code is used to configure: ? either a single ended or differential measurement ? channel to be selected ? power down/reference options
ncd9830 http://onsemi.com 13 msb 6 5 4 3 2 1 0 sd c2 c1 c0 pd1 pd0 x x bit 7: sd ? this configures the type of input to be used. if set to 0 then the device performs a dif ferential measurement. if set to 1 then a single ended measurement is made. bit 6 ? 4: c2 ? c0 ? these are the channel selection bits. see channel selector table below for more detail. bit 3 ? 2: pd1 ? pd0 ? these bits let the use select whether the adc is powered on, off and whether the internal reference is to be used or the external one. see power down selection table 8 for more detail. table 8. power down selection pd1 pd0 description 0 0 power down between adc conversions 0 1 internal reference off, adc on 1 0 internal reference on, adc off 1 1 internal reference on. adc on table 9. channel selector channel selection control sd c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0 0 0 0 +in ? in ? ? ? ? ? ? ? 0 0 0 1 ? ? +in ? in ? ? ? ? ? 0 0 1 0 ? ? ? ? +in ? in ? ? ? 0 0 1 1 ? ? ? ? ? ? +in ? in ? 0 1 0 0 ? in +in ? ? ? ? ? ? ? 0 1 0 1 ? ? ? in +in ? ? ? ? ? 0 1 1 0 ? ? ? ? ? in +in ? ? ? 0 1 1 1 ? ? ? ? ? ? ? in +in ? 1 0 0 0 +in ? ? ? ? ? ? ? ? in 1 0 0 1 ? ? +in ? ? ? ? ? ? in 1 0 1 0 ? ? ? ? +in ? ? ? ? in 1 0 1 1 ? ? ? ? ? ? +in ? ? in 1 1 0 0 +in ? ? ? ? ? ? ? in 1 1 0 1 ? ? ? +in ? ? ? ? ? in 1 1 1 0 ? ? ? ? ? +in ? ? ? in 1 1 1 1 ? ? ? ? ? ? ? +in ? in
ncd9830 http://onsemi.com 14 initiating conversions communication in standard/fast mode communication in standard/fast mode corresponds to a clock speed of 100/400 khz. the device address is sent over the bus followed by r/w set to 0. this is followed by the command byte. if the command byte is correct the device initiates the conversion cycle by turning on the converter circuit after it receives the channel selection bits (sd, c 2 - c 0 ) of the command byte. after receiving the command byte the ncd 9830 sends an acknowledge bit. the device is now ready to be read by the master. frame 2 command byte frame 1 serial bus address byte ack. by ncd9830 sdata sclk start by master sd c2 c1 c0 pd1 pd0 x x 1 0 0 1 0 a1 a0 r/w ack. by ncd9830 1 1 9 9 figure 18. write addressing the device to write the command byte frame 1 serial bus address byte sdata sclk start/restart by master frame 2 first data byte d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 1 0 a1 a0 r/w 1 1 9 9 ack. by ncd9830 stop not ack. by master figure 19. conversation between master and ncd9830 in standard/fast mode serial bus address byte sdata sclk start/restart by master high speed clock holding low during conversion 0 10 0 1 0 a1 a0 r/w 19 ack. by ncd9830 d0 d1 d2 d3 d4 d5 d6 d7 conversion time n.ack. by master stop. by master clock contnues after conversion sdata figure 20. conversation between master and ncd9830 in high speed mode during read operation the device address is sent over the bus followed by r/w set to 1 followed by the acknowledge bit from the slave .data can be read from the device in the form of a 8 bit byte. the msb of the data word is d 7 and lsb is d 0 . communication in high speed mode communication in high speed mode corresponds to a clock speed of 3.4 mhz. master initiates a high speed master code that change the mode from standard/fast to high speed. the high speed master code format is as follows: start 0 0 0 0 1 x x x n.ack the start condition bit is initiated by master and n.ack is initiated by ncd9830. the master code must be run in fast mode to enter in the high speed mode. high speed operation does not give enough time span for a conversion to be completed between the start condition initiated by the master and the read cycle. therefore, in high speed mode ncd9830 stretches the clock at low level after the read cycle is initiated by the master until the conversion is complete. master can decide to remain in high speed mode
ncd9830 http://onsemi.com 15 by initiating a restart condition instead of stop at the end of read sequence. a stop bit at the end of read cycle changes the mode back to the standard/fast. a typical high speed read operation is shown in figure 20 . reference voltage selection the internal reference can be turned on or off depending on the command byte bit pd 1 status. when the device turns on for the first time the internal reference is off. proper settling time must be allowed while switching any reference (external or internal) on or off before any conversion is initiated. depending on the i 2 c operation mode (standard, fast or high speed) the settling time would vary. layout considerations digital boards are electrically noisy environments, and the ncd9830 sar architecture is sensitive to power supply transients, reference voltage variation and other noise sources in the circuit. any sudden transient spike can affect the accuracy of over all conversion result. so care must be taken to minimize noise induced at the device inputs. take the following precautions: ? place a 0.1 f bypass capacitor close to the v dd pin. in extremely noisy environments, where the impedance between the v dd and the power supply is high a bigger capacitor with capacitance value from 1 ? 10 f must be used. ? extra care must be taken while using external reference voltage for the device. using a 5 v external reference voltage may require to connect the i/o ref pin directly to v dd . any transient glitches and spikes will induce a lot of noise in the reference voltage that would compromise the overall performance of the adc. appropriate measures must be taken to avoid pollution of reference voltage. place the component far from the microprocessor or any other digital circuitry to avoid high frequency noise injection in the analog portions of adc. a clean analog ground must be used with a dedicated analog ground plane ordering information device package shipping ? NCD9830DBR2G tssop ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncd9830 http://onsemi.com 16 package dimensions tssop ? 16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncd9830/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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